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ACD2202
CATV/TV/Video Downconverter with Dual Synthesizer
Data Sheet - Rev 2.1
FEATURES
* * * * * * * * * * * Integrated Downconverter Integrated Dual Synthesizer 256 QAM Compatibility Single +5 V Power Supply Operation Low Power Consumption: <0.6 W Low Noise Figure: 8 dB High Conversion Gain: 10 dB Low Distortion: -53 dBc Three-Wire Interface Small Size -40 C to +85 C
APPLICATIONS
* * * * * Set Top Boxes CATV Video Tuners Digital TV Tuners CATV Data Tuners Cable Modems
S8 Package 28 Pin SSOP
PRODUCT DESCRIPTION
The ACD2202 uses both GaAs and Si technology to provide the downconverter and dual synthesizer functions in a double conversion tuner gain block, local oscillator, balanced mixer and dual synthesizer. The specifications meet the requirements of CATV/TV/Video and Cable Modem Data applications. The ACD2202 is supplied in a 28 lead SSOP package and requires a single +5 V supply voltage. The IC is well suited for applications where small size, low cost, low auxiliary parts count and a nocompromise performance is important. It provides for cost reduction by lowering the component and packaged IC count and decreasing the amount of labor-intensive production alignment steps, while significantly improving performance and reliability.
RFD
RF2: 64/65 Prescaler 18 Bit RF2 N Counter RF2 Phase Detector RF2 Charge Pump
CPD
RFIN+ RFINLow Noise VGA
VIF+IFOUT+
REFIN REFOUT
15 Bit RF2 R Counter
VIF+IFOUTMixer
Oscillator 15 Bit RF1 R Counter
Phase Splitter
RFU
RF1: 64/65 Prescaler
18 Bit RF1 N Counter
RF1 Phase Detector
RF1 Charge Pump
CPU
TCKT
OSC OUT
Clock Data Enable
22 Bit Data Registar
Figure 1: Downconverter Block Diagram
12/2003
Figure 2: Dual Synthesizer Block Diagram
ACD2202
1 2 3 4 5 6 7 8 9 10 11 12 13 14
RFIN+ RFINGND ISET TCKT OSCGND OSCGND VSS VSS EN DATA CLK REFIN REFOUT
VIF + IFOUT+ VIF + IFOUTGND VSUP OSCOUT GND GND VSS VSS RFD CPD CPU RFU VSYN
Figure 3: Pinout
28 27 26 25 24 23 22 21 20 19 18 17 16 15
2
Data Sheet - Rev 2.1 12/2003
ACD2202 Table 1: Pin Description
PIN
1
NAME
RFIN+
DESCRIPTION
Downconverter Differential RFInput
PIN
28
NAME
VIF+IFOUT+
DESCRIPTION
Downconverter Differential IFOutput Inductively coupled to +VDD Downconverter Differential IFOutput Inductively coupled to +VDD Downconverter Ground (Must be connected) Oscillator and Phase Splitter Supply (+VDD) Oscillator Output (Connected to Synthesizer RF Input) Downconverter Ground (Must be connected) Downconverter Ground (Must be connected) Synthesizer Ground (Required) Synthesizer Ground (Required) Synthesizer Downconverter RFInput Synthesizer Downconverter Charge Pump Output Synthesizer Upconverter Charge Pump Output Synthesizer Upconverter RFInput Synthesizer Supply (+VDD)
2
RFIN-
Downconverter Differential RFInput Downconverter Ground (Must be connected) Downconverter Gilbert Cell Current Source Resistor Oscillator Input Port (Tank circuit connection) Oscillator Tank Circuit Ground (Not to be connected to any other circuit ground) Same as Pin 6 Synthesizer Ground (Required) Synthesizer Ground (Required) 3-Wire Interface Enable
27
VIF+IFOUT -
3
GND
26
GND
4
ISET
25
VSUP
5
TCKT
24
OSCOUT
6
OSCGND
23
GND
7 8 9 10
OSCGND V SS V SS EN
22 21 20 19
GND V SS V SS RFD
11
DATA
3-Wire Interface Data
18
C PD
12 13 14
C LK REFIN REFOUT
3-Wire Interface Clock Crystal Reference Input Crystal Reference Output
17 16 15
C PU RFU VSYN
Data Sheet - Rev 2.1 12/2003
3
ACD2202
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PARAMETER Supply Voltage (pins 25, 27 & 28) (pin 15) Voltage on pins 10 through 14, 16 through 19 with VSS = 0 V Input Voltages (pins 1, 2 & 5) Input Power (pins 1 & 2) (pin 5) (pins 13, 16 & 19)
MIN -0.3 -55 -
MAX +9 +6.5 VSYN +0.3 0 +10 +17 +20 +150 260 4 40
UNIT VD C VD C VD C dB m C C S ec C/W
Storage Temperature Soldering Temperature Soldering Time Thermal Impedance, JC
Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability.
Table 3: Operating Ranges
PARAMETER Downconverter Frequencies RF Input (RF) IF Output (IF) Local Oscillator (LO)
(1)
MIN 900 35 865 400 400 2 +4.70 -40
TYP 4 +5 -
MAX 1200 150 1350 2100 1400 20 10 +5.25 +85
UNIT
MHz
Synthesizer Frequencies Upconverter Synthesizer (RFU) Downconverter Synthesizer (RFD) Reference Oscillator (REFIN) Phase Detector Supply Voltage: VDD (pins 15, 25, 27, 28) Ambient Operating Temperature: TA
(2)
MHz
VD C C
The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. Notes: (1) Mixer operation is possible beyond these frequencies with slightly reduced performance. (2) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 23-25.
4
Data Sheet - Rev 2.1 12/2003
ACD2202 Table 4: Electrical Specifications - Downconverter Section (7) (TA = 25 C , VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz)
PARAMETER Conversion Gain (1) Conversion Gain (2) SSB Noise Figure (2), (3) Cross Modulation
(2), (4), (6)
MIN 8 11 +12 -10 -
TYP 10 13 4 -56 -90 -5 -10 -48 -50 -10 50 30 400
MAX 14 17 7 -53 -53 -85.5 65 45 550
UNIT dB dB dB c dB c dB m dBc/Hz dB m dB m dB c dB m dB m mA mA mW
3rd Order Intermodulation Distortion (IMD3) (2), (5), (6) 2-Tone 3rd Order Input Intercept Point (IIP3) (2), (5), (6) LO Phase Noise (@ 10 KHz Offset) (1), (2) LO Output Power (pin 24) (1), (2) Spurious @ IF Output LO Signals and Harmonics Beats Within Output Channel Other Beats from 2 to 200 MHz Other Spurious IF Supply Current (pin 27 & 28) (1), (2),(6) Osc/Phase Splitter Supply Current (pin 25) Power Consumption
Notes: (1) As measured in ANADIGICS test fixture with single-ended RF input. (2) As measured in ANADIGICS test fixture with differential RF inputs. (3) SSB noise figure will be approximately 3 dB higher with single-ended RF input. (4) Two tones: 1085 and 1091 MHz, -20 dBm each, 1091 MHz tone AM-modulated 99% at 15 kHz. (5) Two tones: 1085 and 1091 MHz, -15 dBm each. (6) R1 = 10 Ohms. (7) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 23-25.
Data Sheet - Rev 2.1 12/2003
5
ACD2202 Table 5: Electrical Specifications - Synthesizer Section (4) (TA = 25 C , VDD = +5 VDC)
PARAMETER Prescalar Input Sensitivity Upconverter: RFU (pin 16) (1) Downconverter: RFD (pin 19) (2) Upconverter: RFU (pin 16) (1) Downconverter: RFD (pin 19) (2) Reference Oscillator Sensitivity (pin 13) Charge Pump Output Current (3) SINK SOURCE Supply Current Power Consumption MIN -7 -13 -6 -11 TYP 0.5 1.25 -1.25 35 165 MAX +20 +20 50 250 UNIT COMMENTS (over operating frequency) dB m TA = +85 C, VDD = +4.7 V TA = +85 C, VDD = +4.7 V Vp-p
mA mA mW
Notes: (1) Measured at 250 kHz comparison frequency. (2) Measured at 62.5 kHz comparison frequency. (3) CPU and CPD = VCC/2. (4) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 23-25.
6
Data Sheet - Rev 2.1 12/2003
ACD2202 Table 6: Digital Interface Specifications (TA = 25 C, VDD = +5 VDC, ref. Figure 4)
PARAMETER Logic High Input: VH (pins 10, 11, 12) Logic Low Input: VL (pins 10, 11, 12) Logic Input Current Consumption (pins 10, 11, 12) Data to Clock Set Up Time: tCS Data to Clock Hold Time: tCH Clock Pulse Width High: tCWH Clock Pulse Width Low: tCWL Clock to Load Enable Setup Time: tES Load Enable Pulse Width: tEW Rise Time: tR Fall Time: tF
MIN 2.0 50 10 50 50 50 50 -
TYP 10 10
MAX 0.8 0.01 -
UNIT V V mA ns ns ns ns ns ns ns ns
DATA CLOCK
N20: MSB (R20: MSB)
N19 (R19)
N10 R10
N9 (R9) (R8) (C2)
C2
C1: LSB (C1: LSB)
tCWL
LE
OR
LE
tCS
tCH
tCWH
tES
tEW
Figure 4: Serial Data Input Timing
Data Sheet - Rev 2.1 12/2003
7
ACD2202
PERFORMANCE DATA
Figure 5: Typical Conversion Gain and Noise Figure vs. Supply Voltage (TA = +25 C, fLO2 = 1042 MHz)
14.0 3.65 13.8 3.63
Figure 6: Typical Conversion Gain and Noise Figure vs. Ambient Temperature (VDD = +5 V, fLO2 = 1042 MHz)
15.0 5.0 14.0 4.6
Conversion Gain (dB)
Conversion Gain (dB)
Noise Figure (dB)
13.6
3.61
13.0
4.2
13.4
3.59
12.0
3.8
13.2
Conversion Gain Noise Figure
3.57
11.0
Conversion Gain Noise Figure
3.4
13.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3
3.55
10.0 25 35 45 55 65 75 85
3.0
Supply Voltage (V)
Ambient Temperature (C)
Figure 7: Typical Phase Noise at 10 kHz Offset vs. Supply Voltage (TA = +25 C, fLO2 = 1042 MHz)
-90 -91
Figure 8: Typical Phase Noise at 10 kHz Offset vs. Ambient Temperature (VDD = +5 V, fLO2 = 1042 MHz)
-84 -86
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
-92
-88
-93
-90
-94
-92
-95 4.7 4.8 4.9 5.0 5.1 5.2 5.3
-94 25 35 45 55 65 75 85
Supply Voltage (V)
Ambient Temperature (C)
Figure 9: Typical Local Oscillator Output Power vs. Supply Voltage (TA = +25 C, fLO2 = 1042 MHz)
-4.5 -5.0
Figure 10: Typical Local Oscillator Output Power vs. Ambient Temperature (VDD = +5 V, fLO2 = 1042 MHz)
-4.5 -5.0
Output Power (dBm)
Output Power (dBm)
-5.5
-5.5
-6.0
-6.0
-6.5
-6.5
-7.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3
-7.0 25 35 45 55 65 75 85
Supply Voltage (V)
Ambient Temperature (C)
8
Data Sheet - Rev 2.1 12/2003
Noise Figure (dB)
ACD2202
Figure 11: Typical Upconverter Prescaler Sensitivity vs. Local Oscillator Frequency (TA = +25 C, VDD = +5 V)
-5
Figure 12: Typical Downconverter Prescaler Sensitivity vs. Local Oscillator Frequency (TA = +25 C, VDD = +5 V)
-12
Prescalar Sensitivity (dBm)
-15
Prescalar Sensitivity (dBm)
700 900 1100 1300 1500 1700 1900 2100
-10
-14
-16
-20
-18
-25
-20
-30
-22
-35 500
-24 400
600
800
1000
1200
1400
LO1 Frequency (MHz)
LO2 Frequency (MHz)
Figure 13: Typical Upconverter Prescaler Sensitivity vs. Supply Voltage (TA = +25 C, fLO1 = 2100 MHz)
-7.0
Figure 14: Typical Downconverter Prescaler Sensitivity vs. Supply Voltage (TA = +25 C, fLO2 = 1000 MHz)
-16.0
Prescalar Sensitivity (dBm)
Prescalar Sensitivity (dBm)
4.7 4.8 4.9 5.0 5.1 5.2 5.3
-7.5
-16.5
-8.0
-17.0
-8.5
-17.5
-9.0
-18.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3
Supply Voltage (V)
Supply Voltage (V)
Figure 15: Typical Upconverter Prescaler Sensitivity vs. Ambient Temperature (VDD = +5 V, fLO1 = 2100 MHz)
-6.0
Figure 16: Typical Downconverter Prescaler Sensitivity vs. Ambient Temperature (VDD = +5 V, fLO2 = 1000 MHz)
-15.0
Prescalar Sensitivity (dBm)
-6.5
Prescalar Sensitivity (dBm)
-15.5
-7.0
-16.0
-7.5
-16.5
-8.0
-17.0
-8.5 25 35 45 55 65 75 85
-17.5 25 35 45 55 65 75 85
Ambient Temperature (C)
Ambient Temperature (C)
Data Sheet - Rev 2.1 12/2003
9
ACD2202
Figure 17: Typical Conversion Gain and Noise Figure vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V, fLO2 = 1042 MHz)
15 5.0 14
C o n v e rs io n G a in (d B )
Figure 18: Typical Total Current Consumption vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V)
200 180
Conversion Gain Noise Figure
4.6
N o is e F ig u re (d B )
13
4.2
Current (mA)
160
140
12
3.8
120
11
3.4
100
10 0 5 10 15 20 25
3.0
80 0 5 10 15 20 25
R1 Resistor Value (W )
R1 Resistor Value (W )
Figure 19: Typical Input IP3 vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V)
19
-50
Figure 20: Typical Cross Modulation vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V)
Cross Modulation (dBc)
0 5 10 15 20 25
17
-55
IIP3 (dBm)
15
13
-60
11
9
-65 0 5 10 15 20
R1 Resistor Value (W )
R1 Resistor Value (W )
10
Data Sheet - Rev 2.1 12/2003
ACD2202
LOGIC PROGRAMMING
Synthesizer Register Programming The ACD2202 includes two PLL synthesizers. Each synthesizer contains programmable Reference and Main dividers, which allow a wide range of local oscillator frequencies. The 22-bit registers that control the dividers are programmed via a shared three-wire bus, consisting of Data, Clock and Enable lines. The data word for each register is entered serially in order with the most significant bit (MSB) first and the least significant bit (LSB) last. The rising edge of the Clock pulse shifts each data value into the register. The Enable line must be low for the duration of the data entry, then set high to latch the data into the register. (See Figure 4.) Register Select Bits The two least significant bits of each register are register select bits that determine which register is programmed during a particular data entry cycle. Table 7 indicates the register select bit settings used to program each of the available registers. Table 7: Register Select Bits
S E LE C T BITS S 2 0 0 1 1 S 1 0 1 0 1
DESTINATION REGISTER FOR SERIAL DATA
Reference Divider Register for PLL2 Main Divider Register for PLL2 Reference Divider Register for PLL1 Main Divider Register for PLL1
Reference Divider Programming The reference divider register for each synthesizer consists of fifteen divider bits, five program mode bits and the two register select bits, as shown in Table 8. The fifteen divider bits allow a divide ratio from 3 to 32767, inclusive, as shown in Table 9.
MSB
Table 8: Reference Divider Registers
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
LSB
22
1
Program Mode D 5 D 4 D 3 D 2 D 1 R 15 R 14 R 13
Reference Divider Divide Ratio, R R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1
Select S 2 S 1
Table 9: Reference Divider R Counter Bits
DIVIDE RATIO R 3 4 32767 R 15 0 0 1 R 14 0 0 1 R 13 0 0 1 R 12 0 0 1 R 11 0 0 1 R 10 0 0 1 R 9 0 0 1 R 8 0 0 1 R 7 0 0 1 R 6 0 0 1 R 5 0 0 1 R 4 0 0 1 R 3 0 1 1 R 2 1 0 1 R 1 1 0 1
Notes: Divide ratios less than 3 are prohibited.
Data Sheet - Rev 2.1 12/2003
11
ACD2202 Main Divider Programming The main divider register for each synthesizer consists of seven A counter bits, eleven B counter bits, two program mode bits and the two register select bits, as shown in Table 10. The main divider divide ratio, N, is determined by the values in the A and B counters. The eleven B Counter bits and allowed values are shown in Table 11, and the seven A Counter bits and allowed values are shown in MSB
22 21 20 19 18 17 16
Table 12. Note that there are some limitations on the ranges of the values for each counter. Pulse Swallow Function The VCO output frequency for the local oscillator is computed using the following equation; the variables are defined in Table 13: fVCO = N x fOSC/R, where N = [(P x B) + A] LSB
8 7 6 5 4 3 2 1
Table 10: Main Divider Registers
15 14 13 12 11 10 9
Program Mode C 2 C 1 B 11 B 10 B 9 B 8
B Counter B 7 B 6 B 5 B 4 B 3 B 2 B 1 A 7 A 6
A Counter A 5 A 4 A 3 A 2 A 1
Select S 2 S 1
Table 11: Main Divider B Counter Bits
VALUE OF B COUNTER 3 4 2047
B 11 0 0 1
B 10 0 0 1
B 9 0 0 1
B 8 0 0 1
B 7 0 0 1
B 6 0 0 1
B 5 0 0 1
B 4 0 0 1
B 3 0 1 1
B 2 1 0 1
B 1 1 0 1
Notes: B > A, Divide ratios less than 3 are prohibited.
Table 12: Main Divider A Counter Bits
VALUE OF A COUNTER 0 1 127
Notes: B > A, A < P
Table 13: Variable Definitions
A 1 0 1 1
A 7 0 0 1
A 6 0 0 1
A 5 0 0 1
A 4 0 0 1
A 3 0 0 1
A 2 0 0 1
VAR fVCO B A fOSC R P
DEFINITION Desired output frequency of external voltage controlled oscillator (VCO) Divide ratio of B counter (3 to 2047) Divide ratio of A counter (0 < A < P, A < B) Frequency of external reference crystal or oscillator Divide ratio of R counter (3 to 32767) Preset modulus of prescalar (P = 64)
12
Data Sheet - Rev 2.1 12/2003
ACD2202 Programmable Modes Each register contains bits set aside for programming different modes of operation in the synthesizers. Currently, the only programmable mode is the polarity of the phase detector in each of the synthesizers. Bit D1 in each reference divider register controls this feature. Bits D2 through D5 in the reference divider registers and bits C1 and C2 in the main divider registers are reserved for future use, and have no current function. They can be set Table 14: Phase Detector Polarity Bit either high or low without affecting synthesizer performance. Setting Phase Detector Polarity Table 14 shows how bit D1 of each reference divider register controls the polarity of the phase detector associated with each PLL. The correct setting is determined by using Table 15 and Figure 21. Figure 21: VCO Characteristics
S 2 0 1
S 1 0 0
D 1 PLL2 Phase Detector Polarity PLL1 Phase Detector Polarity
VCO OUTPUT FREQUENCY
(1)
Table 15: Phase Detector Polarity Selection D 1 0 1 PHASE DETECTOR POLARITY Negative Positive VC O CHARACTERISTICS (SEE FIGURE 12) curve (2) curve (1)
(2)
VCO INPUT VOLTAGE
Synthesizer Programming Example The following example for programming the two synthesizers in the ACD2202 details the calculations used to determine the required value of each bit in all four registers: Requirements Desired CATV input channel: "HHH" - 499.25 MHz picture carrier (501 MHz digital channel center frequency) (Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency) First IF frequency: 1087.75 MHz Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz Phase detector comparison frequency for up converter: 250 KHz Crystal reference oscillator frequency: 4 MHz Calculation of Reference Divider Values The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired phase detector comparison frequency: R = fOSC / fPD For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison frequency are used to yield RPLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter R counter are RPLL2 = 000000001000000.
Data Sheet - Rev 2.1 12/2003
13
ACD2202 For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison frequency are used to yield RPLL1 = 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter are RPLL1 = 000000000010000. Calculation of Main Divider Values The values for the A and B counters are determined by the desired VCO output frequency for the local oscillator and the phase detector comparison frequency: N = fVCO / f PD B = trunc(N / P) A = N - (B x P)
The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example. The main divider ratio for the down converter, then, is NPLL2 = 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the ACD2202, BPLL2 = trunc(16672 / 64) = 260, and APLL2 = 16672 - (260 x 64) = 32. These results give bit values of BPLL2 = 00100000100 and APLL2 = 0100000 for the B and A counters. The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example. Therefore, NPLL1 = 1587 MHz / 250 KHz = 6348, BPLL1 = trunc(6348 / 64) = 99, and APLL1 = 6348 - (99 x 64) = 12. These results give bit values of BPLL1 = 00001100011 and APLL1 = 0001100 for the B and A counters. Phase Detector Polarity Assuming the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be negative, and D1PLL1 = 1. If the VCO for the down converter has a positive slope, the phase detector polarity for PLL2 should be positive, and D1PLL2 = 0. In summary, for this example, the four register programming words are shown in Tables 16 and 17: Table 16: PLL1 and PLL2 Reference Divider Register Bits for Synthesizer Programming Example
MSB
LSB
22
21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Program Mode D 5 0 0 D 4 0 0 D 3 0 0 D 2 0 0 D 1 1 0 R 15 0 0 R 14 0 0 R 13 0 0 R 12 0 0
Reference Divider R Counter R 11 0 0 R 10 0 0 R 9 0 0 R 8 0 0 R 7 1 0 R 6 0 0 R 5 0 1 R 4 0 0 R 3 0 0 R 2 0 0 R 1 0 0
Select S 2 0 1 S 1 0 0
MSB
Table 17: PLL1 and PLL2 Main Divider Register Bits for Synthesizer Programming Example
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
LSB
22
1
Program Mode C 2 0 0 C 1 0 0 B 11 0 0 B 10 0 0 B 9 1 0
Main Divider B Counter B 8 0 0 B 7 0 1 B 6 0 1 B 5 0 0 B 4 0 0 B 3 1 0 B 2 0 1 B 1 0 1 A 7 0 0
Main Divider A Counter A 6 1 0 A 5 0 0 A 4 0 1 A 3 0 1 A 2 0 0 A 1 0 0
Select S 2 0 1 S 1 1 1
14
Data Sheet - Rev 2.1 12/2003
ACD2202
APPLICATION INFORMATION
VSYN 20 kW VSYN pins 16,19 AV~ -1000 VSS VSS pins 17,18
VSYN 200 W
pin 13 VSS VSYN pin 14 VSS 300 kW
pin 1 pin 2
5 kW pin 4 GND
5 kW GND
VSUP 10 W 15 W 5W GND 10 pF OSCGND
pin 27 5 pF
pin 28 5 pF 5W GND
pin 24 pin 5
Figure 22: Equivalent Circuits
Data Sheet - Rev 2.1 12/2003
15
ACD2202
Figure 23: PC Board Layout Top View
Figure 24: PC Board Layout Mid View
RF
RF
IF Balun AFC Out
4M Hz Xtal
ACD2202 J1 LO In
1
Figure 25: PC Board Layout Bottom View Table 18: J1 Header Pinout PIN 1 2 3 4 5 6 16 FUNCTION Clock Data Ground Enable +5 V DC +30 V DC
Data Sheet - Rev 2.1 12/2003
Figure 26 Evaluation Fixture Table 19: Fixture Pinout
PIN RF RF IF AFC Out LO In FU N C TION D ownconverter RF Input D ownconverter RF Input IF Output (Si ngle Ended) To Upconverter Osci llator Tuni ng C i rcui t Synthesi zer RFU LO Input
IF
L3
C24 DT1
+5V 1
RF RF
C1 C2
2
RFIN+ RFINGND ISET TCKT OSCGND OSCGND VSS VSS EN DATA CLK REFIN REFOUT ACD2202 R8 L2 C13 C12 C11 C10 C9 C14 RFU VSYN CPU
17 16 15
VIF + IFOUT+ VIF + IFOUTGND 26 VSUP OSC OUT GND GND VSS VSS RFD CPD
18 19 20 21 22 23 24 25 27
28
C21
C22
C23
R1
4 5
3
R13 C18 C16 C20 C17 R11 Q1 C19
+30V
J1
7
D1 L1
8 9 10
C3
6
6
+30V
5
+5V
4
R5 R3
11
Figure 27: Evaluation Fixture Schematic
R12 R4
12 13 14
Data Sheet - Rev 2.1 12/2003
R6 X1
+5V
3
R2
2
1
AFCOUT LOIN
C4 R7
C5
C6
R9
R10
C15
C7
C8
ACD2202
17
ACD2202 Table 20: Evaluation Fixture Parts List
ITEM # C 1, C 2, C 20 C3 C 7, C 8 C 12 C9, C11, C 14, C 21, C 22 C 10, C 23 C 15, C 17 C 16 C 18 C 19 C 24 C 13 C 4, C 5, C6 R8 R5 R2, R3, R4 R12 R11 R7 R13 R10 R1
VALUE 100pF 9pF 30pF 220uF .1uF
SIZE 0603 0603 0603
DESCRIPTION Chip-capacitor Chip-capacitor Chip-capacitor
PART #
GRM39COG101J50V GRM39COG090C50V GRM39COG300J50V PCE2040CT-ND GRM39Y5V104Z16V
QTY
3
VENDOR Murata Murata Murata DIGI-KEY Murata
1 2 1
10V VA Capacitor Series 0603 Chip-capacitor
5
1000pF 4700pF 1uF .01uF 10uF 15pF 5600pF 33pF 51 10K 2K 1K 2.7K 3K 22K 8.2K 10
0603 0603 0603 0603 35 V TANT 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
Chip-capacitor Chip-capacitor Radial-lead Chip-capacitor Chip-capacitor
GRM39X7R102K50V GRM39X7R472K25V RPE113-X7R-105-K-050 GRM39X7R103K25V
2 2 1
Murata Murata Murata Murata DIGI-KEY Murata Murata Murata Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic
1 1
TE Series Cap. PCS6106CT-ND Chip-capacitor Chip-capacitor Chip-capacitor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor
GRM39COG150J50V GRM39X7R562K50V GRM39COG330J50V ERJ-3GSYJ510 ERJ-3GSYJ103 ERJ-3GSYJ202 ERJ-3GSYJ102 ERJ-3GSYJ272 ERJ-3GSYJ302 ERJ-3GSYJ223 ERJ-3GSYJ822
1 1 3
1 1 3 1 1 1 1 1 1
ERJ-3GSYJ100
18
Data Sheet - Rev 2.1 12/2003
ACD2202 Table 20: Evaluation Fixture Parts List continued
ITEM # R6, R9 L1 L2 L3 D1 DT1 Q1 X1 VALUE 0 5.6nH 68nH 270nH 1S V 245 4:1 30V SMD 4MHZ SOT-23 SIZE 0603 0805 0805 0805 DESCRIPTION Chip Resistor Inductor Inductor Inductor Varactor diode Transformer Transistor NPN Darl. Crystal PART #
ZC0603 0805CS-050X-BC 0805CS-680X-BC 0805CS-271X-BC 1SV245 ETC4-1-2 FMMTA13CT-ND SE2618CT-ND
QTY
2 1 1 1 1 1
VENDOR RCD Coilcraft Coilcraft Coilcraft Toshiba M/A-COM, Inc. North America DIGI-KEY DIGI-KEY
1
1
Data Sheet - Rev 2.1 12/2003
19
ACD2202
PACKAGE OUTLINE
Figure 28: S8 Package Outline - 28 Pin SSOP
20
Data Sheet - Rev 2.1 12/2003
ACD2202
NOTES
Data Sheet - Rev 2.1 12/2003
21
ACD2202
NOTES
22
Data Sheet - Rev 2.1 12/2003
ACD2202
NOTES
Data Sheet - Rev 2.1 12/2003
23
ACD2202
ORDERING INFORMATION
ORDER NUMBER A C D 2202S 8P 1 A C D 2202S 8P 0 TEMPERATURE RANGE -40C to +85C -40C to +85C PACKAGE DESCRIPTION 28 Pin SSOP 28 Pin SSOP COMPONENT PACKAGING Tape & Reel, 3500 pieces per reel Tubes, 50 pieces per tube
ANADIGICS, Inc. 141 Mount Bethel Road Warren, New Jersey 07059, U.S.A Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com
IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product's formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS product in any such application without written consent is prohibited.
24
Data Sheet - Rev 2.1 12/2003

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